Programmer’s Model
3.3Register descriptions
The following registers are described in this section:
•GIRFCR: [15] (+ 0x00)
•GIRTXGENCR: [16] (+ 0x04) on page 3-6
•GIRRXGENCR: [16] (+ 0x08) on page 3-7
•GIRTXDUTYCR: [4] (+ 0x0c) on page 3-8
•GIRSTAT: [8] (+0x10) on page 3-8
•GIRDATAR: [18/17] (+ 0x14c) on page 3-9
•GIRIIR/GIRICR: [3/0] (+0x18) on page 3-10.
For each of the following register descriptions, the format of the title is:
Register name: [bit width] (Offset from Base)
3.3.1GIRFCR: [15] (+ 0x00)
GIRFCR is the function control register which acts as the main source of control for the infrared interface. Separate enables are provided for transmit and receive paths. In addition, the FIFOs can be separately enabled. Table 3-2 shows the bit assignments for the GIRFCR.
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Table 3-2 GIRFCR register read/write bits |
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Bits |
Name |
Type |
Function |
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31:15 |
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Read/write |
Reserved, do not modify, read as 0. |
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14 |
RORIntEnable |
Read/write |
Receive overrun interrupt enable bit. |
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1 |
= Interrupt is enabled whenever receive |
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overrun bit is set. |
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0 |
= Interrupt is disabled. |
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13 |
RxIntEnable |
Read/write |
Receive interrupt enable bit. |
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1 |
= Interrupt is enabled. |
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0 |
= Interrupt is disabled. |
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12 |
TxIntEnable |
Read/write |
Transmit interrupt enable bit. |
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1 |
= Interrupt is enabled. |
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0 |
= Interrupt is disabled. |
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3-4 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM DDI 0149B |
Programmer’s Model
Table 3-2 GIRFCR register read/write bits (continued)
Bits |
Name |
Type |
Function |
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11 |
TxIntCtrl |
Read/write |
Transmit interrupt control bit. |
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1 |
= When transmit function is enabled, |
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GIRTXINTR is raised when transmitter is not |
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busy, that is when transmission has completed |
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and TxIntEnable = 1. |
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0 |
= GIRTXINTR raised when transmit FIFO is |
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half full or less, independent of whether the |
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transmit function is enabled or disabled, but |
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TxIntEnable must be 1. |
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10 |
RxIntCtrl |
Read/write |
Receive interrupt control bit. |
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1 |
= When receive function is enabled, |
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GIRRXINT is raised when the receive FIFO is |
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not empty and RxIntEnable = 1. |
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0 |
= When receive function is enabled, |
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GIRRXINT is raised when receive FIFO is half |
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full or greater and RxIntEnable = 1. |
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9 |
TxEnable |
Read/write |
Enable transmit function. |
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1 |
= Enable transmission. |
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0 |
= Disable transmission. |
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8 |
RxEnable |
Read/write |
Enable receive function. |
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1 |
= Enable receiver. |
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0 |
= Disable receiver. |
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7 |
TxFifoEn |
Read/write |
Enable transmit FIFO. |
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1 |
= Transmit FIFO enabled to accept data. |
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0 |
= Transmit FIFO disabled and flushed. |
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6 |
RxFifoEn |
Read/write |
Enable receive FIFO. |
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1 |
= Receive FIFO enabled to accept data. |
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0 |
= Receive FIFO disabled and flushed. |
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5 |
ModEn |
Read/write |
Enable modulation. |
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1 |
= Output level is modulated with a carrier |
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signal as described below. |
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0 |
= Output level is set by bit 16 of the transmit |
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FIFO. |
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ARM DDI 0149B |
© Copyright ARM Limited 1999. All rights reserved. |
3-5 |
Programmer’s Model
Table 3-2 GIRFCR register read/write bits (continued)
Bits |
Name |
Type |
Function |
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4 |
DemodEn |
Read/write |
Enable demodulation. |
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1 = Demodulation enabled. |
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0 = Demodulation disabled. |
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3:2 |
EdgeCtrl[1:0] |
Read/write |
Edge detector control bits for pulse timer in |
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receive direction: |
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00 |
= Edge detection disabled. |
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01 |
= Enable falling edges to restart timer. |
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10 |
= Enable rising edges to restart timer. |
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11 = Either edge restarts timer (used in |
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demodulation mode). |
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1:0 |
Winctrl[1:0] |
Read/write |
Limit control bits for window comparator: |
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00 |
= Limits set to +3 and -3. |
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01 |
= Limits set to +3 and -4. |
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10 |
= Limits set to +4 and -3. |
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11 = Limits set to +4 and -4. |
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3.3.2GIRTXGENCR: [16] (+ 0x04)
GIRTXGENCR is the transmit clock generator control register which holds the value of the divisor to be applied to the internal programmable divider for transmit functions.
When the transmit function is disabled, the value written to this register is applied directly to the internal programmable transmit clock divider. When the transmit function is enabled, changes to this register value only take effect when the associated internal counter reaches zero.
Table 3-3 on page 3-7 shows the bit assignments for the GIRTXGENCR.
3-6 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM DDI 0149B |
Programmer’s Model
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Table 3-3 GIRTXGENCR register read/write bits |
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Bits |
Name |
Type |
Function |
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31:16 |
- |
Read/write |
Reserved, do not modify, read as 0. |
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15:0 |
clkdiv |
Read/write |
Divisor value for the programmable divider/clock |
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generator. |
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Value of 0 is reserved. |
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Divisor value = (clkdiv + 1). |
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If the value of clkdiv is 1, the divisor value is 2. |
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If the value of clkdiv is 2, the divisor value is 3, |
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and so on, up to a maximum divisor value of |
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65536. |
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3.3.3GIRRXGENCR: [16] (+ 0x08)
GIRRXGENCR is the receive clock generator control register which holds the value of the divisor to be applied to the internal programmable divider for receive functions.
When the receive function is disabled, the value written to this register is applied directly to the internal programmable receive clock divider. When the receive function is enabled, changes to this register value only take effect when the associated internal counter reaches zero. Table 3-4 shows the bit assignments for the GIRRXGENCR.
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Table 3-4 GIRRXGENCR register read/write bits |
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Bits |
Name |
Type |
Function |
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31:16 |
- |
Read/write |
Reserved, do not modify, read as 0. |
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15:0 |
clkdiv |
Read/write |
Divisor value for the programmable divider/clock |
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generator. |
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Value of 0 is reserved. |
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Divisor value = (clkdiv + 1). |
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If the value of clkdiv is 1, the divisor value is 2. |
If the value of clkdiv is 2, the divisor value is 3, and so on, up to a maximum divisor value of 65536.
ARM DDI 0149B |
© Copyright ARM Limited 1999. All rights reserved. |
3-7 |