07.Sequential circuits
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Chapter 7 − Sequential Circuits |
Page 31 of 37 |
(e)). Finally, the complete modulo-6 up counter circuit is shown in Figure 24(e). Comparing this circuit with the circuit from Example 9.3 shown in
C= 0 |
Q2Q1Q0 = 000 |
C= 1 |
Q2Q1Q0 = 001 |
C= 0 |
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Y = 0 |
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Y = 0 |
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C= 1 |
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C= 1 |
Q2Q1Q0 = 101 |
C= 0 |
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C= 0 |
Q2Q1Q0 = 010 |
Y = 1 |
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Y = 0 |
C= 1 |
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C= 1 |
C= 0 |
Q2Q1Q0 = 100 |
C= 1 |
Q2Q1Q0 = 011 |
C= 0 |
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Y = 0 |
Y = 0 |
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(a) |
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Current State |
Next State |
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Q2next |
Q1next Q0next |
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Q2Q1Q0 |
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C = 0 |
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C = 1 |
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000 |
000 |
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001 |
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001 |
001 |
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010 |
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010 |
010 |
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011 |
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011 |
011 |
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100 |
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100 |
100 |
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101 |
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101 |
101 |
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000 |
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(b)
Current State |
Implementation |
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D2 |
D1 D0 |
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Q2Q1Q0 |
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C = 0 |
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C = 1 |
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000 |
000 |
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001 |
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001 |
001 |
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010 |
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010 |
010 |
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011 |
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011 |
011 |
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100 |
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100 |
100 |
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101 |
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101 |
101 |
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000 |
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(c)
(f) where D flip-flops are used, it is obvious that using T flip-flops for this problem result in a much smaller circuit than using D flip-flops.
Microprocessor Design – Principles and Practices with VHDL |
Last updated 7/18/2003 1:19 PM |
Chapter 7 − Sequential Circuits |
Page 32 of 37 |
7.8Exercises
9.1 Design a modulo-4 Counter using T flip-flops
9.2. Design a FSM that counts the following decimal sequence
3, 7, 2, 6, 3, 7, 2, 6, …
The count is to be represented directly by the contents of the D flip-flops. The counting starts when the control input C is asserted and stops whenever C is de-asserted. Assume that the next-state from all unused states is the state for the first count in the sequence, i.e. the state for 3.
9.3 Design a counter that counts in the following sequence:
1, 4, 6, 7, 1, 4, 6, 7, ….
The count is to be represented directly by the contents of the flip-flops. Use a JK flip-flop, a D flip-flop and a SR flip-flop in this order starting from the most significant bit for the three flip-flops needed. The counter is enabled by the input C. The count stops when C = 0. The next-state from all unused states are undefined.
Microprocessor Design – Principles and Practices with VHDL |
Last updated 7/18/2003 1:19 PM |
Chapter 7 − Sequential Circuits |
Page 33 of 37 |
7.9Selected Answers
9.1 Next-state table:
Current State |
Next State |
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Q1next Q0next |
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Q1 Q0 |
C = 0 |
C = 1 |
00 |
00 |
01 |
01 |
01 |
10 |
10 |
10 |
11 |
11 |
11 |
00 |
Implementation table:
Current State |
Next State |
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T1 T0 |
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Q1 Q0 |
C = 0 |
C = 1 |
00 |
00 |
01 |
01 |
00 |
11 |
10 |
00 |
01 |
11 |
00 |
11 |
Circuit: |
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Excitation equations: |
C |
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T1 = CQ0 |
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T0 = C |
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T1 |
Q1 |
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Clk |
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Q'1 |
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T0 |
Q0 |
Clk |
Clk |
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Q'0 |
9.2Since we’re using the flip-flop content to represent the count and the largest number is 7, therefore, we need three (3) bits even though there are only four numbers in the sequence.
State diagram:
C = 0 |
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C = 0 |
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011 |
C = 1 |
111 |
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C = 1 |
xxx |
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all unused |
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state |
C = 1 |
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110 |
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010 |
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C = 1 |
C = 0 |
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C = 0 |
Microprocessor Design – Principles and Practices with VHDL |
Last updated 7/18/2003 1:19 PM |
Chapter 7 − Sequential Circuits |
Page 34 of 37 |
Next-state table and implementation table:
Current State |
Next State / Implementation |
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Q2next Q1next Q0next / D2D1D0 |
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Q2Q1Q0 |
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C = 0 |
C = 1 |
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000 |
011 |
011 |
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001 |
011 |
011 |
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010 |
010 |
110 |
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011 |
011 |
111 |
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100 |
011 |
011 |
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101 |
011 |
011 |
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110 |
110 |
011 |
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111 |
111 |
010 |
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Excitation equations:
D2 = Q2'Q1C + Q2Q1C' |
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D1 = 1 |
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D0 = Q1' + Q2'Q0 + Q0C' + Q2Q0'C |
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Circuit: |
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C |
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D2 |
Q2 |
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Clk |
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Q'2 |
'1' |
D1 |
Q1 |
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Clk |
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Q'1 |
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D0 |
Q0 |
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Clk |
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Clk |
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Q'0 |
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Microprocessor Design – Principles and Practices with VHDL |
Last updated 7/18/2003 1:19 PM |
Chapter 7 − Sequential Circuits
9.3 Next-state table:
Current State |
Next State |
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Q2next |
Q1next Q0next |
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Q2Q1Q0 |
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C = 0 |
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C = 1 |
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001 |
001 |
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100 |
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100 |
100 |
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110 |
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110 |
110 |
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111 |
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111 |
111 |
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001 |
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Excitation tables for the three flip-flops:
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Q |
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Qnext |
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J |
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K |
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D |
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S |
R |
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0 |
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0 |
0 |
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× |
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0 |
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0 |
× |
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0 |
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1 |
1 |
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× |
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1 |
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1 |
0 |
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1 |
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0 |
× |
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1 |
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0 |
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0 |
1 |
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1 |
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1 |
× |
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0 |
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1 |
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× |
0 |
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Implementation table: |
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Current State |
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Implementation |
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J2 K2 |
D1 S0 R0 |
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Q2Q1Q0 |
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C = 0 |
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C = 1 |
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001 |
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0× 0× 0 |
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1× 001 |
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100 |
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× |
000× |
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× |
010× |
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110 |
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× |
010× |
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× |
0110 |
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111 |
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× |
01× 0 |
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× |
10× 0 |
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K-maps and excitation equations:
J2 |
CQ2 |
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Q1Q0 |
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00 |
01 |
11 |
10 |
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00 |
× |
× |
× |
× |
C |
01 |
0 |
× |
× |
1 |
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11 |
× |
× |
× |
× |
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10 |
× |
× |
× |
× |
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J2 = C |
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S0 |
CQ2 |
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Q1Q0 |
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00 |
01 |
11 |
10 |
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00 |
× |
0 |
0 |
× |
CQ1 |
01 |
× |
× |
× |
0 |
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11 |
× |
× |
× |
× |
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10 |
× |
0 |
1 |
× |
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S0 = CQ1 |
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K2 |
CQ2 |
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Q1Q0 |
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00 |
01 |
11 |
10 |
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00 |
× |
0 |
0 |
× |
CQ0 |
01 |
× |
× |
× |
× |
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11 |
× |
0 |
1 |
× |
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10 |
× |
0 |
0 |
× |
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K2 = CQ0 |
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R0 |
CQ2 |
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Q1Q0 |
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00 |
01 |
11 |
10 |
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00 |
× |
× |
× |
× |
CQ1' 01 0 |
× |
× |
1 |
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11 |
× |
0 |
0 |
× |
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10 |
× |
× |
0 |
× |
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R0 = CQ1' |
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Page 35 of 37
D1 |
CQ2 |
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Q1Q0 |
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00 |
01 |
11 |
10 |
CQ0' 00 × |
0 |
1 |
× |
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C'Q1 |
01 |
0 |
× |
× |
0 |
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11 |
× |
1 |
0 |
× |
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10 |
× |
1 |
1 |
× |
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D1 = CQ0' + C'Q1 |
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Circuit: |
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Microprocessor Design – Principles and Practices with VHDL |
Last updated 7/18/2003 1:19 PM |
Chapter 7 − Sequential Circuits |
Page 36 of 37 |
C |
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J 2 |
Q2 |
Clk |
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K2 |
Q'2 |
D1 |
Q1 |
Clk |
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Q'1 |
S0 |
Q0 |
Clk |
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R0 |
Q'0 |
Clk |
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Microprocessor Design – Principles and Practices with VHDL |
Last updated 7/18/2003 1:19 PM |
Chapter 7 − Sequential Circuits
Index
A
Algorithmic state machine chart. See ASM chart Analysis of sequential circuit, 4
ASM chart, 18
C
Characteristic equation, 5
E
Excitation equation, 5
F
Finite-state machine, 2
FSM. See Finite-state machine.
M
Mealy FSM, 2
Microprocessor next-state logic, 2 state memory, 2
Page 37 of 37
Moore FSM, 2
N
Next-state equation, 5
Next-state logic, 2
Next-state table, 5
O
Output equation, 5
Output table, 6
S
Sequential circuit analysis, 4 synthesis, 10
State, 2
State action table, 18, 20 State diagram, 6
State memory, 2
Synthesis of sequential circuit, 10
Microprocessor Design – Principles and Practices with VHDL |
Last updated 7/18/2003 1:19 PM |