Sec. 5.5 |
Chapter Summary |
263 |
(b) If Q1 is biased at the edge of saturation, calculate the value of IS.
13.The circuit of Fig. 5.113 must be designed for an input impedance of greater than 10 k and
VCC = 2.5 V
Q 1
R 2
Figure 5.113
a gm of at least 1=(260 ). If = 100, IS = 2 10,17 A, and VA = 1, determine the minimum allowable values of R1 and R2.
14.Repeat Problem 13 for a gm of at least 1=(26 ). Explain why no solution exists.
15.We wish to design the CE stage depicted in Fig. 5.114 for a gain (= gmRC) of A0 with an
VCC
Q 1
R 2
Figure 5.114
output impedance of R0. What is the maximum achievable input impedance here? Assume
VA = 1.
16. The circuit of Fig. 5.115 is designed for a collector current of 0.25 mA. Assume IS =
|
VCC = 2.5 V |
R 1 |
R C 3 kΩ |
|
10 k Ω |
Q 1 |
|
R2 |
Ω |
|
RE = 200 |
Figure 5.115
6 10,16 A, = 100, and VA = 1.
(a)Determine the required value of R1.
(b)What is the error in IC if RE deviates from its nominal value by 5%?
17.In the circuit of Fig. 5.116, determine the maximum value of R2 that guarantees operation of Q1 in the active mode. Assume = 100, IS = 10,17 A, and VA = 1.
18.Consider the circuit shown in Fig. 5.117, where IS1 = 2IS2 = 5 10,16 A, 1 = 2 = 100, and VA = 1.
(a)Determine the collector currents of Q1 and Q2.
(b)Construct the small-signal equivalent circuit.