1 лаба AMI / алфимыч

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15.09.2023 11:00:31
// Design Name:
// Module Name: coder_ananyev
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module coder_ananyev(
input clk,
input stud_number,
input reset,
//output logic result,
output logic result0,
output logic result1,
output logic result2,
output logic result3
);
logic sign = 0;
logic [1:0] counter = 0;

/* always@(posedge clk or negedge reset) begin
if(!reset)begin
result <= 0;
end
else begin
if (!stud_number) result <= 0;
else if (stud_number) begin
counter <= counter + 1;
if (counter > 0 && counter < 3)result <= 1;
else result <= 0;
end
if (counter == 4'd0 && stud_number) sign <= sign + 1;
end
end */

always@(posedge clk or negedge reset) begin
if(!reset)begin
//result <= 0;
result0 <= 0;
result1 <= 1;
result2 <= 1;
result3 <= 0;
end
else begin
if (!stud_number) begin
result0 <= 0;
result1 <= 0;
result2 <= 0;
result3 <= 0;
end
else if (stud_number) begin
result0 <= 0;
result1 <= 1;
result2 <= 1;
result3 <= 0;
sign <= sign + 1;
end
// if (counter == 4'd0 && stud_number) sign <= sign + 1;
end
end

endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15.09.2023 11:02:13
// Design Name:
// Module Name: coder_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module coder_tb();
logic clk = 0;
logic reset = 0;
logic stud_number;

initial begin
stud_number = 1; reset = 0;
#1;
stud_number = 1; reset = 1;
#1;
stud_number = 1;
#1;
stud_number = 1;
#1;
stud_number = 1;
#1;
stud_number = 1;
#1;
stud_number = 0;
#1;
stud_number = 1;
#1;
stud_number = 0;
#1;
stud_number = 0;
#1;
stud_number = 0;
#1;
stud_number = 0;
#1;
stud_number = 0;
#1;
stud_number = 1;
#1;
stud_number = 1;
#1;
stud_number = 1;
#1;
stud_number = 0;
#1;
stud_number = 0;
#1;
stud_number = 0;
#1;
stud_number = 1;
#1;
stud_number = 1;
#1;
stud_number = 0;
#1;
stud_number = 1;
#5 $finish;
end


coder_ananyev u_coder_ananyev(
.stud_number (stud_number),
.clk (clk),
.reset (reset)
);

always
#0.5 clk = !clk;


endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.10.2023 10:46:17
// Design Name:
// Module Name: decoder_ananyev
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module decoder_ananyev(
input logic result0,
input logic result1,
input logic result2,
input logic result3,
input logic sign,
output logic decoder_result
);

logic [4:0] coder_result;

assign coder_result [0] = result0;
assign coder_result [1] = result1;
assign coder_result [2] = result2;
assign coder_result [3] = result3;
assign coder_result [4] = sign;

always_comb begin
case (coder_result)
5'b10110 : decoder_result = 1'b1;
5'b00000 : decoder_result = 1'b0;
5'b10000 : decoder_result = 1'b0;
5'b00110 : decoder_result = 1'b1;
default : decoder_result = 1'bx;

endcase

end



endmodule